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MRF49XA
3.9.1
SETTING INTERRUPTS
3.9.1.4
WUTINT: Wake-up Timer Interrupt
The device’s interrupt pin (IRO) signals one of eight
interrupt events to the host microcontroller. The
interrupt source in the microcontroller is read out from
the transceiver through the SDO pin. The interrupt
sources that are available are briefly described in the
following subsections.
This interrupt occurs when the time specified by the
wake-up timer has elapsed. It is valid only when the
WUTEN bit (PMCREG<1>) is set. The device
periodically wakes up and switches to Receive mode. If
valid FSK data is received, the device sends an
interrupt to the microcontroller and continues filling the
3.9.1.1
TXRXFIFO: Transmit Register or
Receive FIFO bit
RXFIFO. After the completion of transmission, the
FIFO is read out completely and all other interrupts are
cleared. The device returns to the Low-Power
1.
2.
Transmit mode: Transmit Register Ready bit
This interrupt is generated when the Transmit
register is empty. It is valid only when the
TXDEN bit (GENCREG<7>) is set and the
TXCEN bit (PMCREG<5>) is enabled.
Receive mode: Receive FIFO Empty bit
Consumption mode.
3.9.1.5 LCEXINT: Logic Low-Level Change
on External Interrupt
Follows the level of the INT pin if configured as an
external interrupt by clearing the FINTDIO bit
(RXCREG<10>).
This interrupt is generated when the bit level in
the RXFIFOREG has reached the
3.9.1.6
LBTD: Low Battery Threshold Detect
preprogrammed level. An interrupt is triggered
when the number of received data bits in the
receiver FIFO reaches the threshold set by the
FFBC bits (FIFORSTREG<7:4>). This is valid
only when the FIFOEN bit (GENCREG<6>) is set
This interrupt occurs when V DD goes below the
programmable low battery detector threshold level
configured by the LBDVB bits (BCSREG<3:0>). It is
valid only when the LBDEN bit (PMCREG<2>) is set.
and the RXCEN bit (PMCREG<7>) is enabled.
3.9.2
CLEARING INTERRUPTS
3.9.1.2 POR: Power-on Reset Interrupt
The POR interrupt is generated when a change on the
V DD line triggers an internal Reset circuit or a Software
Reset was issued. For details, see Section 3.1, Reset .
If any of the interrupt sources gets active, the IRO
changes to logic low level and the corresponding
interrupt bit in the status byte goes high. Clearing an
interrupt implies:
? releasing the IRO pin to return to logic high, and
3.9.1.3
TXOWRXOF: Transmit Overwrite
Receive Overflow bit
? clearing the corresponding interrupt bit in the
STSREG
1.
2.
Transmit mode: Transmit Register Underrun or
Overwrite bit
This interrupt is generated when the automatic
Baud Rate Generator (BRG) has completed the
transmission of a byte in TXBREG before the
register write . It is valid only when the TXDEN bit
(GENCREG<7>) is set and the TXCEN bit
(PMCREG<5>) is enabled.
Receive mode: Receive FIFO Overflow bit
The clearing of each of the interrupts is briefly
described in the following subsections.
3.9.2.1 TXRXFIFO
1. Transmit mode
The IRO pin and its status bit remain active until
the register is written (if underrun does not occur
until the register write) or the transmitter and the
TX latch are switched off.
This interrupt is generated when the bits
received are more than the FIFO capacity
(16 bits). This is valid only when the FIFOEN bit
(GENCREG<6>) is set and the RXCEN bit
(PMCREG<7>) is enabled.
2.
Receive mode
The IRO pin and its status bit remain active until
the FIFO is read (receive FIFO interrupt
threshold number of bits have been read). The
receiver is switched off or the RXFIFO is
switched off.
3.9.2.2
POR
The IRO pin and its status bit are cleared by reading the
Status Read register.
? 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 53
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